1. Field of the Invention
The present invention relates to a latch circuit for temporarily storing and successively outputting data corresponding to an input signal and to a register circuit having a plurality of stages of the latch circuits.
2. Description of the Related Art
With reference to FIG. 1, a conventional register circuit and a clock signal for controlling the register circuit will be described.
Referring to FIG. 1, two stages of latch circuits are disposed as a master side latch circuit and a slave side latch circuit. The master side latch circuit and the slave side latch circuit are connected. At a leading edge of a clock signal CLK, input data is received from a data input terminal IN and output from a register output terminal OUT. As shown in FIG. 1, when the signal level of the clock signal CLK is low, the master side latch circuit directly outputs the input data to a connection point Pm. The slave side latch circuit receives the input data from the connection point Pm and latches the input data.
When the signal level of the clock signal CLK is high, the register circuit shuts out the input data of the master side latch circuit and holds (latches) inner data Pm. However, since the slave side latch circuit becomes a through state, the slave side latch circuit still outputs the inner data Pm to an output terminal OUT. Since the signal level of the clock signal CKL alternatively changes from high to low, when the signal level of the clock signal CLK changes from low to high, the data is output to the output terminal OUT.
Next, for simplicity, the structure of the master side latch circuit will be described. The input data is input to an input transfer circuit composed of a PMOS M31 and an NMOS M32 whose drain and source are connected in parallel. The clock signal CLK and an inverted clock signal CLKB are input to the gate of the PMOS M31 and the NMOS M32 of the input transfer circuit, respectively. An output terminal of the transfer circuit is connected to an output driving inverter INV 31. The inverter INV 31 outputs data to the connection point Pm. The data that is output from the connection point Pm is input to an inverter INV 32. Output data of the inverter INV 32 is output to a hold transfer circuit composed of a PMOS M33 and an NMOS M34. An output terminal of the hold transfer circuit is connected to the input terminal of the inverter INV 31.
The clock signals CLKB and CLK are input to the gates of the PMOS M33 and the NMOS M34 of the hold transfer circuit, respectively. This structure applies to the slave side latch circuit. In the slave side latch circuit, input data is input from the connection point Pm and data is output from the output terminal OUT. On the slave side latch circuit, however, the clock signals CLK and CLKB are input to NMOS transistors and PMOS transistors, respectively. In other words, the clock signals CLK and CLKB are input to an NMOS M35 and a PMOS M36 of the input transfer circuit, respectively. The clock signals CLK and CLKB are input to an NMOS M37 and a PMOS M38 of the hold transfer circuit, respectively.
When the latch circuit is in the through state, the input transfer circuit is turned on and the hold transfer circuit is turned off. Thus, the input data can be output to the connection point of the latch circuit through one inverter. On the other hand, when the latch circuit is in the latch state, the input transfer circuit is turned off and the hold transfer circuit is turned on. Thus, in the latch state, the input data is shut out. Just before the latch state takes place, the output data is output to the input terminal of the output inverter through the hold inverter. Thus, the data can be held in a flip-flop structure.
The latch circuit is switched between the latch state and the through state with the clock signals CLK and CLKB. A register circuit is composed of two latch circuits that are connected in series in such a manner that the clocks signals CLK and CLKB are input to the latch circuits in the reverse relation. Corresponding to the high and low levels of the clock signals, the register circuit successively outputs input data.
Tanaka et al. have disclosed a flip-flop circuit as Japanese Patent Laid-Open Publication No. 60-198919 (hereinafter referred to as first related art reference). The flip-flop circuit is a one-bit flip-flop circuit used as a driving circuit for an LCD (Liquid Crystal Display) apparatus. The flip-flop circuit is a register circuit composed of a first (master) latch circuit and a second (slave) latch circuit. With a logic circuit using a clock signal and a control signal, both the latch circuits are placed in a through state. The flip-flop circuit has a circuit structure for switching between a synchronous function for receiving data corresponding to a clock edge and an asynchronous function for directly receiving data asynchronous to the clock signal. However, this flip-flop circuit does not handle a low frequency input signal and a high frequency input signal. In addition, the circuit does not operate with only the synchronous function.
Noisshiki et. al. have disclosed a flip-flop circuit for a high speed logic frequency circuit as Japanese Patent Laid-Open Publication No. 5-160682 (hereinafter referred to as second related art reference). In the second related art reference, a clock signal is used in common with an input transfer circuit and a hold transfer circuit.
In the conventional register circuits, two transfer circuits (namely, gates of four MOS transistors) should be switched for each latch circuit. When a register is composed of two latch circuits, the load of eight transistors is applied to a clock signal as a control signal. Since a latest large scale LSI having many input/output signals use many registers, the load applied to the clock signal is very heavy. In addition, as the operation frequency of the LSI is rising, it is necessary to drive each register at high speed and prevent registers from skewing with the clock signal.
Thus, in the conventional register circuits, viewed from a clock signal, the capacitance between the gate and source of the input transfer circuit and the capacitance between the gate and drain of the hold transfer circuit tend to become large. This problem is a drawback that restricts the high speed operation of the register circuits.
In other words, the clock signal that is input to a register should drive four transfer circuits that are a data receiving master side input transfer circuit, a data releasing slave side input transfer circuit, a data latching master side hold transfer circuit, and a data latching slave side hold transfer circuit. These transfer circuits are essential for the operation of the register. However, since these transfer circuits are driven with one clock signal and an inverted clock signal thereof, the load applied thereto becomes large.
An object of the present invention is to allow a clock signal that is input to a latch circuit including an input transfer circuit and a hold transfer circuit and a register circuit composed of a plurality of stages of latch circuits to be improved.
A first aspect of the present invention is a latch circuit for temporarily storing an input signal and successively outputting the input signal, comprising an input transfer circuit for inputting and outputting the input signal corresponding to a reference clock signal supplied to a control gate of said input transfer circuit, a first inverter for inverting an output signal of the input transfer circuit, a second inverter for inverting an output signal of the first inverter, and a hold transfer circuit for inputting an output signal of the second inverter and outputting it to the first inverter, wherein a second clock signal is input to the gate of the hold transfer circuit, the signal level of the second clock signal becoming high with a predetermined delay against a leading edge of the reference clock signal and becoming low corresponding to a trailing edge of the reference clock signal.
A second aspect of the present invention is a register circuit, comprising a plurality of latch circuits disposed in a plurality of stages, wherein each of the plurality of latch circuits has an input transfer circuit for inputting a reference clock signal, a first inverter for inverting an output signal of the input transfer circuit, a second inverter for inverting an output signal of the first inverter, and a hold transfer circuit for inputting an output signal of the second inverter and outputting it to the first inverter, wherein a first stage latch circuit is a master side register circuit, wherein the input transfer circuit is connected to an output terminal of the second inverter so as to form a slave side register circuit, and wherein a third clock signal is input to the gate of the hold transfer circuit of the master side register circuit, the signal level of the third clock signal becoming high with a predetermined delay against a leading edge of the reference clock signal and becoming low corresponding to a trailing edge of the reference clock signal.
A third aspect of the present invention is a latch circuit for temporarily storing an input signal and successively outputting the input signal, comprising a first switch for taking in the input signal by ON, a first clock generator for generating a first clock and controlling ON/OFF of said first switch, a hold circuit for holding the input signal through said first switch and, after that, outputting the input signal, and a second clock generator for generating a second clock and controlling an ON/OFF operation of said hold circuit, wherein the second clock is different from the first clock by predetermined phase.
According to the present invention, signals for controlling the transfer circuit of the master side latch circuit and the slave side latch circuit of the register circuit are generated corresponding to respective clock signals, when these signals are operated at a high frequency, they are turned of f. Thus, the load of the clock signal lines for controlling the operation of the register is reduced. In addition, the data releasing operation of the register is performed at high speed. Moreover, when the register is operated at a high frequency, the power consumption of the register can be suppressed from increasing.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.